In the case of semiconductor devices using lead technology, the chip-specific resistance is continually being reduced by miniaturization of the structures of the semiconductor elements with their number simultaneously being increased, with the result that there is a need also to reduce the size of the connections and dimensions of the required housings, or packages, while at the same time reducing the “package resistance”, both from an electrical standpoint and from a thermal standpoint.
Electronic power devices have been described which comprise a semiconductor chip having a plurality of MOS transistors. On the plurality of source electrodes, a corresponding plurality of thermocompression heads are bonded as so-called “stud bumps.” Arranged on the stud bumps is a common connecting plate as source connection in the form of a prestressed clip.
This structure of the common source connection has the disadvantage that a tool is required for applying thermocompression heads, so that the distance between the connections cannot be decreased arbitrarily, or the number of connections to the source electrodes cannot be increased arbitrarily, in order to further reduce the “package resistance”. Moreover, a clip construction has the further disadvantage of contact transition resistances. Furthermore, the structure has the disadvantage that a serial production method has to be used for the application of the plurality of source connections, which limits the throughput and impedes mass production.
Other methods use solder pastes on the active top side of the semiconductor chip for connecting gate internal leads and source internal leads to the corresponding electrodes of the semiconductor elements. These methods have the disadvantage that the distance between the common gate electrode and the source electrodes is limited and cannot be decreased further in order to ensure that the solder paste does not cause a short circuit in the course of sintering together. Moreover, on account of different solder thicknesses, the process implementation of solder pastes constitutes a risk with regard to tilting of the semiconductor chip and with regard to introduction of additional contaminants.